This invention generally relates to semiconductor memory devices and technology, and in particular to two terminal NDR elements and static random access memory (SRAM) devices that utilize such elements.
The rapid growth of the semiconductor industry over the past three decades has largely been enabled by continual advancements in manufacturing technology which have allowed the size of the transistor, the basic building block in integrated circuits (ICs), to be steadily reduced with each new generation of technology. As the transistor size is scaled down, the chip area required for a given circuit is reduced, so that more chips can be manufactured on a single silicon wafer substrate, resulting in lower manufacturing cost per chip; circuit operation speed also improves, because of reduced capacitance and higher transistor current density. State-of-the-art fabrication facilities presently manufacture ICs with minimum transistor lithographically defined feature size smaller than 100 nm, so that microprocessor products with transistor counts approaching 100 million transistors per chip can be manufactured cost-effectively. High-density semiconductor memory devices have already reached the gigabit scale, led by dynamic random access memory (DRAM) technology. The DRAM memory cell consists of a single pass transistor and a capacitor (1T/1C), wherein information is stored in the form of charge on the capacitor. Although the DRAM cell provides the most compact layout (with area ranging between 4F2 and 8F2, where F is the minimum feature size), it requires frequent refreshing (typically on the order of once per millisecond) because the charge on the capacitor leaks away at a rate of approximately 10xe2x88x9215 Amperes per cell. This problem is exacerbated by technology scaling, because the transistor leakage current increases with decreasing channel length, and also because a reduction in cell capacitance results in a smaller number of stored charge carriers, so that more frequent refreshing is necessary. Thus, scaling of DRAM technology to much higher densities presents significant technological challenges.
Static RAM (SRAM) does not require refreshing and is generally faster than DRAM (approaching 1 ns access times as compared to tens of ns for DRAM). However, the SRAM cell is more complex, requiring either four n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and two p-channel MOSFETs, or four n-channel MOSFETs and two polycrystalline-silicon (poly-Si) load resistors, resulting in significantly larger cell size (typically greater than  greater than 120 F2). Innovations which provide significant reductions in SRAM cell size while allowing the SRAM cell to retain its favorable operating characteristics are therefore highly desirable.
Negative differential resistance (NDR) devices have previously been proposed for compact static memory applications. E. Goto in IRE Trans. Electronic Computers, March 1960, p. 25 disclosed an SRAM cell consisting of two resonant tunneling diodes (RTDs) and a pass transistor. For a variety of NDR devices including RTDs, the current first increases with increasing applied voltage, reaching a peak value, then decreases with increasing applied voltage over a range of applied voltages, exhibiting negative differential resistance over this range of applied voltages and reaching a minimum (xe2x80x9cvalleyxe2x80x9d) value. At yet higher applied voltages, the current again increases with increasing applied voltage. Thus, the current-vs.-voltage characteristic is shaped like the letter xe2x80x9cNxe2x80x9d. A key figure of merit for NDR devices is the ratio of the peak current to the valley current (PVCR). The higher the value of the PVCR, the more useful the NDR device is for variety of circuit applications. The PVCR of RTDs is generally not high enough to make it practical for low-power SRAM application, because in order for the RTDs in a Goto cell to have sufficient current drive, the valley current is too large, causing large static power dissipation. In addition, RTDs require specialized fabrication process sequences so that the complexity of an integrated RTD/MOSFET SRAM process would be substantially higher than that of a conventional complementary MOS (CMOS) SRAM process, resulting in higher manufacturing cost.
Accordingly, there exists a significant need for NDR devices with very high ( greater than 106) PVCR which can be easily integrated into a conventional CMOS technology, for compact, low-power, low-cost SRAM.
A new type of SRAM device to achieve such functionality using Negative Differential Resistance Field Effect Transistors (NDR FETs) is described in detail in a patent application Ser. No. 10/029,077 filed Dec. 21, 2001 by T J King and assigned to the present assignee, and published on May 9, 2002 as Publication No. 2002/0054502. The NDR FET structure, operation and method of making the same are discussed in detail in patent application Ser. No. 09/603,101 filed Jun. 22, 2000 by King et al., which is also assigned to the present assignee. Such details are also disclosed in a corresponding PCT application PCT/US01/19825 which was published as publication no. WO 01/99153 on Dec. 27, 2001. The above materials are hereby incorporated by reference.
Additional embodiments of such device are clearly advantageous for use in memory applications, particularly embedded memory.
An object of the present invention is to provide an improved type of negative differential resistance (NDR) element to complement the types of devices available for providing a negative differential resistance characteristic in a silicon based environment;
A further object of the present invention is to provide a static random access memory (SRAM) cell which utilizes such types of new NDR elements.
For achieving these objects, one aspect of the invention provides a two terminal negative differential resistance (NDR) semiconductor device formed on a silicon-based substrate. The two terminal NDR device includes a first doped region; a second doped region; and a gate adapted for receiving a gate control signal. The gate includes a gate electrode coupled to the first doped region. A controllable conductance region coupled between the first and second doped regions, said controllable conductance region being configured such that when a first bias potential is applied to the gate electrode and a second bias potential is applied between the first doped region and second doped region, energetic carriers are generated. A portion of these energetic carriers are trapped by a dielectric layer located proximate to the gate and forming an interface with the controllable conductance region. The device is configured to trap a number of the energetic carriers at or near the interface preferably using low energy level traps. Accordingly, in such device, a number of energetic carriers that can be trapped in the dielectric layer can be controlled by adjusting the first bias potential and/or the second bias potential so that the two terminal NDR semiconductor device operates as a silicon-based NDR device.
In a preferred embodiment, the two terminal NDR semiconductor device is an NDR-capable field effect transistor (FET) which has a negative voltage threshold, and whose gate is coupled to a drain region formed in the silicon substrate. In this manner, the two terminal NDR semiconductor device operates essentially as an NDR diode.
Again, in a preferred embodiment, the controllable conductance region is a channel associated with the NDR capable FET, and which includes a first dopant that is of opposite type to a second dopant used in said first doped region and said second doped region. The charge trapping sites are also preferably characterized by an energy level that is above the conduction band edge of said channel.
In one exemplary application, the two terminal NDR semiconductor device is used as a load element within a memory cell. In such case (and in other applications) the device is coupled to a three terminal NDR semiconductor device on a common silicon substrate, where the three terminal NDR semiconductor device includes an NDR-capable field effect transistor. Furthermore, in a related aspect, the dielectric layer is used for forming charge trapping regions for both the two terminal NDR semiconductor device and the three terminal NDR semiconductor device. Further in a preferred embodiment of such type the two terminal NDR semiconductor device and three terminal NDR semiconductor device include a first channel region and a second channel region, and are formed so that the second channel region includes a concentration of doping impurities that is substantially higher than the first channel region.
Further aspects of the present invention are directed to methods of making and operating the aforementioned two terminal NDR device.
Another aspect of the invention pertains to a memory device utilizing the aforementioned two terminal NDR device as a load element. This memory device comprises a transfer field effect transistor (FET) configured to receive and/or transfer a data value from a data line to a storage node in response to a write and/or read signal respectively provided to the memory cell; and a first negative differential resistance element, the first NDR element being in the form of an NDR-capable field effect transistor (FET) configured to receive a first gate bias signal and having a first NDR FET drain terminal coupled to the storage node, and a first NDR FET source terminal coupled to a first voltage potential at a first node; and a second negative differential resistance element, the second NDR element being a two terminal NDR-capable device configured so that a first terminal receives a second bias signal from a second voltage potential at a second node, and a second terminal is coupled to the storage node. In this fashion, the memory cell uses the negative differential resistance characteristic of the first NDR element and the second NDR element to store the data value at the storage node.
In a preferred embodiment, the first NDR element and the second NDR element are connected in series and are formed in a common substrate and with one or more common layers formed with the transfer FET.
In a preferred approach, the NDR element includes a second NDR FET that has a negative threshold voltage; however, in some embodiments, the second NDR element includes a silicon based tunneling diode. To achieve a diode like operation, the second NDR FET includes a channel doping that is substantially less than that of the first NDR FET. Further in a preferred embodiment, the first NDR element and second NDR element both use a charge trapping region that is located at an interface between an insulation layer and a substrate for each of the elements. However, in some applications, these elements use different types of charge trapping regions, such that a first charge trapping region is located within an insulation layer, while a second charge trapping region is located at an interface between such insulation layer and the substrate.
A method of operating and making the memory cell are also provided to achieve the above objects and others.